A Fast-Locking Digital PLL: Using integrated and differentiator controlling VHDL-AMS and Matlab/Simulink Modeling and Simulations
نویسندگان
چکیده
In this paper we are using new method called “A fast –locking digital DPLL using integrator and diffentiator controlling with VHDL AMS and Matlab. This method reduces the locking Time and improves performance of DPLL. In the Previous method the fast locking DPLL operation Reduces the lock time by a factor about 4.10 Compared to its conventional DPLL counterpart. But the proposed method more effective to reduce locking time with few nano second. It has less computational complexity compare to the previous method.
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